The present technique relates to an apparatus, memory controller, memory module and method for controlling data transfer in memory.
Within modern data processing systems, it is known to provide a memory controller for controlling access to a portion of memory. Hence, access requests from one or more sources may be routed to the memory controller, which then sends appropriate commands to the portion of memory to cause read and write operations to be performed in order to process the access requests. For a read operation, the read data is returned from the memory to the memory controller, and for a write operation the write data is output from the memory controller to the memory.
Often the portion of memory controlled by the memory controller will be formed of a plurality of memory modules, and the memory controller can perform read or write operations to each of the memory modules.
Memory access operations can incur significant power consumption and introduce significant latency, and accordingly it is desirable to seek to provide improved techniques for performing data transfer in memory.